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If precise hole size tolerance is required, the clearance between punch and die should be very close; the die hole should be only 0.002 to 0.004 in. larger than the punch for paper-based materials (Fig. 35.2 and Table 35.2). Glass-based laminates generally require about one-half that tolerance. Dies have, however, been constructed with as much as 0.010 in. all-around clearance between punch and die. They are for use where inspection standards permit rough-quality holes. A die with sloppy clearances is less expensive than one built for precision work, and wide clearance between punch and die causes correspondingly more break and less shear than a tight die will cause.The result is a hole with a slight funnel shape that makes insertion of components easier. FIGURE 35.2 Example of proper tolerance of a Always pierce with the copper side up. Do not use piercpunch and die. ing on designs with circuitry on both sides of the board, because lifting of pads would probably occur. 35.2.4 Hole Location and Size Designs having holes whose distance from the edge of the board or from other holes approaches the thickness of the material are apt to be troublesome. Such designs should be avoided; but when distances between holes must be small, build the best die possible. Use tight clearance between punch and die and punch and stripper, and have the stripper apply plenty of pressure to the work before the punch starts to enter. If the distance between

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EXAMPLE 6-3 Using the results of Example 6-1, nd the components of the Einstein tensor in the coordinate basis. SOLUTION 6-3 We begin by calculating the components of the Ricci tensor. For now, we continue working in the orthonormal basis. Therefore, we use

already lead-free; however, stud bumping is typically limited to a smaller die and those with a small number of I/O count requirements (note that I/O here refers to the total number of connections required across the die and the carrier/substrate). Furthermore, the stud-bumpbased lead-free solution has its challenges due to the serial nature of the stud-bumping and die-attach processes. Consequently, a lot of effort continues to go into the development of lead-free solder-based wafer bumping. Lead-free wafer bumping is discussed in more detail in the next section.

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4.6.3.4 Wafer Bumping. Wafer bumping is a wafer-level packaging technology that uses solder bumps to form interconnects between the integrated circuit (IC or chip) and the actual package. To create a solderable site with an electromigration barrier, the manufacturer usually first deposits an under-bump metallurgy (UBM) of electroless nickel and gold directly onto the I/O pad of the IC. Other typical UBM consists of a 20 50 nm of evaporated chromium acting as contact and adhesion layer, a diffusion barrier of 100 200 nm of Cr:Cu, a conductive layer of 0.4 0.6 mm of copper, and finally an optional oxide protector of about 100 nm of gold.This is followed by the placement of solder either by evaporation, electroplating, or screen printing onto each I/O site and a thermal reflow to form a solder ball as shown in Fig. 4.11.

Under bump metallurgy (UBM)

Flip-chip ball grid array (FCBGA) is a package type that uses solder bumping to yield areaarray interconnectionArea-array interconnection ensures signal and power/ground integrity far more superior to conventional peripheral wire-bonding interconnection due to elimination of wirebond inductance and a lower electrical resistance Solder bumping enables the realization of CSPs CSPs are well accepted in handheld consumer products such as cellular phones and PDAs, since the package size is of vital importance However, the ultimate package is a true chip size package, the wafer-level CSPs (WL-CSP) WL-CSP is predicted to enjoy the highest continuous aggregated growth rate (CAGR) of more than 20 percent since it enables high-performance microprocessor chip (MPU), application-specific integrated circuit (ASIC), and memory devices for the high-end computing and networking markets Bumped die for FCOB assembly is common in electronic manufacturing due to the saving in the printed circuit board real estate.

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